
module multiplier (
    input res_high,
    input src_word,
    input src1_sign,
    input src2_sign,
    input [63:0] src1,
    input [63:0] src2,
    output logic [63:0] res
);

  logic [63:0] usrc1, usrc2;
  logic [63:0] minus_src1, minus_src2;
  logic src1_ltz, src2_ltz, res_ltz;
  logic [127:0] ures, sres;

  always_comb begin
    minus_src1 = 'b0 - src1;
    minus_src2 = 'b0 - src2;
    usrc1 = src1;
    usrc2 = src2;
    if (src_word) begin
      src1_ltz = src1_sign & src1[31];
      src2_ltz = src2_sign & src2[31];
      usrc1[`WORD_BITS-1:32] = 'b0;
      usrc2[`WORD_BITS-1:32] = 'b0;
      usrc1[31:0] = src1_ltz ? minus_src1[31:0] : src1[31:0];
      usrc2[31:0] = src2_ltz ? minus_src2[31:0] : src2[31:0];
    end else begin
      src1_ltz = src1_sign & src1[63];
      src2_ltz = src2_sign & src2[63];
      usrc1 = src1_ltz ? minus_src1 : src1;
      usrc2 = src2_ltz ? minus_src2 : src2;
    end
    res_ltz = src1_ltz ^ src2_ltz;
    ures = usrc1 * usrc2;
    sres = res_ltz ? ('b0 - ures) : ures;
    res = res_high ? sres[127:64] : sres[63:0];
    if (src_word) res[63:32] = {32{res[31]}};
  end


endmodule
